`include "common_header.verilog" 
//  *************************************************************************
//  File : marker_latch.v
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited.
//  Copyright (c) 2008 MorethanIP
//  Muenchner Strasse 199, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Denis Poverennyy
//  info@morethanip.com
//  *************************************************************************
//  Description : 100G PCS Alignment Marker Detection
//  Marker Latch block is comparing incomming blocks against specified marker
//  if any marker detected searching is stopped 
//  Version     : $Id: marker_latch.v,v 1.2 2014/10/20 08:05:56 dk Exp $
//  *************************************************************************

module marker_latch (reset,
   clk,
   data_val,
   block_lock,
   sw_reset,
   data_in,
   sh_in,
   marker_det,
   vl_enc,
   vl_match);

input   reset;          //  async active high reset
input   clk;            //  system clock
input   data_val;       //  Data and Sync header valid
input   block_lock;     //  Lock state reached
input   sw_reset;       //  Software reset
input   [63:0] data_in; //  Data input
input   [1:0] sh_in;    //  Sync header
input   marker_det;     //  any alignment marker detected
input   [23:0] vl_enc;  //  virtual lane number encoding
output   vl_match; 
// -----------------------------------
//  System
// -----------------------------------
reg     vl_match; 
wire    vl_match_nxt; 

assign vl_match_nxt = data_in[55:32] == ~vl_enc & data_in[23:0] == vl_enc & sh_in == 2'b 01 ? 1'b 1 : 1'b 0;



always @(posedge clk or posedge reset)
   begin : process_1
   if (reset == 1'b 1)
      begin
      vl_match <= 1'b 0;	
      end
   else
      begin
      if (block_lock == 1'b 1 & data_val == 1'b 1 & 
	marker_det == 1'b 0)
         begin
         vl_match <= vl_match_nxt;	
         end
      else if (sw_reset == 1'b 1 )
         begin
         vl_match <= 1'b 0;	
         end
      end
   end


endmodule // module marker_latch

